Published August 11, 2017
| Version v1
Technical note
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FE-I4 Firmware Development and Integration with FELIX for the Pixel Detector
Description
CERN has planned a series of upgrades for the LHC. The last in this current series of planned upgrades is designated the HL-LHC. At the same time, the ATLAS Experiment will be extensively changed to meet the challenges of this upgrade (termed as the "Phase-II" upgrade). The Inner Detector will be completely rebuilt for the phase-II. The TRT, SCT and Pixel will be replaced by the all-silicon tracker, termed as the Inner Tracker (ITk). The read-out of this future ITk detector is an engineering challenge for the routing of services and quality of the data. This document describes the FPGA firmware development that integrates the GBT, Elink and Rx-Tx Cores for communication between the FE-I4 modules and the FELIX read-out system.
Other
Abbreviations: FE-I4 Pixel ChipOther
Abbreviations: FELIX is Front-End Link eXchange FPGA FirmwareFiles
report.pdf
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Additional details
Identifiers
- CDS Report Number
- CERN-STUDENTS-Note-2017-047