Test Bench for the Readout Electronics of the Liquid-Argon Calorimeters of the ATLAS Detector and Development of FPGA Algorithms for Energy Reconstruction under High Pileup Conditions

At CERN, physicists perform various experiments to probe the Standard Model of particle physics and search for new phenomena. The Large Hadron Collider (LHC) creates high energy particle collisions, which experiments like the general-purpose ATLAS detector explore. Since the start of data taking in 2010, numerous milestones have been achieved including the discovery of the Higgs boson in 2012. To increase the event rates and record larger data sets, an LHC high-luminosity upgrade will be installed during a shutdown from 2026 to 2028. In the same period, the ATLAS collaboration commissions the so-called Phase-II upgrade, to exploit the full potential of the LHC. For the ATLAS liquid argon (LAr) calorimeter subsystem this means replacing huge parts of the readout electronics. The completely new Liquid Argon Signal Processor (LASP) boards play a key role. They host powerful FPGAs for signal processing, so that energy deposits in the detector cells and their timing can be reconstructed with high precision. This thesis presents contributions to the software, firmware, and hardware development for the Phase-II upgrade of the LAr calorimeter system. It describes Phase-II  updates applied to the ATLAS Readout Electronics Upgrade Simulation Framework (AREUS) and discusses gain switching simulation studies based on these. It is shown for the whole energy range and different detector regions that the resolution of the upgraded on-detector electronics does not significantly contribute to the total  calorimeter resolution. Implications on the choice of the energy reconstruction algorithm for the different gains are discussed. In particular, scenarios with Optimal Filters (OFs) and Artificial Neural Networks (ANNs) are compared. On the firmware front, several algorithms developed for the LASP FPGA data processing core are introduced. These include designs to detect preamplifier saturation, select gains, correct the signal baseline, reconstruct energy and time, encode data, as well as a combined prototype. One focus is a Convolutional Neural Network (CNN) implementation for energy reconstruction and the optimizations applied to process 12 data streams in parallel with 100 parameters per CNN. For all algorithms behavioural simulations verify the implementations and compilations prove the feasibility on the selected FPGAs in terms of resource usage and running frequency. All algorithms support the two different FPGA models for the LASP test boards and the prototype and final boards. Furthermore, the outcome of three hardware test campaigns with LASP test boards are summarized. Functionality is verified with the very first samples of two LASP test board versions. Eye diagrams and bit error rate measurements of the optical links for various interfaces are presented. These demonstrate the reliability of links on the LASP main blade for data rates up to 25 Gbps. They highlighted the importance of the long copper traces to the optical transceivers on the rear transition module, which are now considered in the prototype board design.