Accelerating Online Selection Algorithms for Level-1 Trigger Scouting in the CMS Phase-2 Upgrade

The Level-1 (L1) Trigger Scouting is a novel real-time data collection system being introduced as part of the L1 trigger of the CMS experiment at the CERN Large Hadron Collider (LHC). While an initial demonstrator implementation already exists, the full-scale scouting system will become a key component of the L1 trigger only with the major Phase-2 upgrade planned for the High-Luminosity LHC (HL-LHC) era. The main motivation for implementing such a system is to search for physics signatures that would evade the traditional trigger and analysis chain. The extreme pile-up conditions foreseen at the HL-LHC are accompanied by a significant upgrade of the entire CMS detector, its readout electronics, and the L1 trigger itself. In particular, the latter will be capable of running sophisticated algorithms that were previously impossible at L1, thus providing reconstructed L1 objects with a resolution comparable to offline processing. By leveraging the enhanced quality of L1 objects and the vast statistics provided by the 40 MHz bunch crossing rate, the L1 Trigger Scouting system enables real-time physics analyses that would be technically and economically unfeasible if relying on full detector data. Beyond a data acquisition infrastructure, the scouting system requires a computing farm to execute its dedicated algorithms. This allows for the exploration of a wide range of compute units and platforms, including CPUs, GPUs, and recently commercialized heterogeneous devices like AMD Versal SoCs, which integrate a Processing System (PS), Programmable Logic (PL), and Adaptable Intelligent (AI) engines on the same chip. This work focuses on exploring how Versal devices can be integrated into the scouting system to offload algorithms originally designed for CPUs and/or FPGAs. In particular, a cut-based search for the rare W boson decay into three charged pions is used as a test case and ported to AI engines. Moreover, a hardware implementation of the final design is tested on an AMD VCK5000 Versal Development Card powered by a VC1902 chip.