Reliability of Advanced Nanoscale CMOS Technology for High-Radiation Environments

Ionizing and non-ionizing radiation is known to cause damage to electronic components, resulting in reduced performance and possible failure. This is a major issue for any application where electronics operate in a radioactive environment. An extreme example is the future High Luminosity Large Hadron Collider (HL-LHC) at CERN, where a Total Ionizing Dose (TID) of 1 Grad (SiO₂) and fluences of 10¹⁶ particles/cm² will be reached in the inner layers of particle detectors after 10 years of operation. The radiation levels in question are orders of magnitude higher than those typically encountered in space applications and require a careful and dedicated investigation of radiation effects in the CMOS technologies used in the Application-Specific Integrated Circuits (ASICs) designed for particle detectors. This thesis explores several topics related to the qualification of technologies for use in CERN particle detector electronics. The results of an unprecedented monitoring effort on dozens of chips in the 130–65 nm CMOS technologies used for ASICs developed for the HL-LHC detectors are discussed. This study revealed extreme fab-to-fab and lot-to-lot variability in the TID response of the technologies used. This investigation demonstrated that TID-induced variability must be taken into account in the design and qualification phases of developments. Displacement damage effects on two 28 nm CMOS technology processes were investigated through proton and neutron irradiation up to the fluences of interest for high-energy physics applications. The study revealed that the observed radiation-induced degradation was caused by the amount of total ionizing dose deposited during neutron and proton exposure, rather than by displacement damage. These results support that 28 nm CMOS technology is suitable for applications in CERN particle detectors. The potential susceptibility of this technology to dose-rate effects is another aspect to be evaluated. Evidence of Enhanced Low-Dose-Rate Sensitivity (ELDRS) in TID-induced leakage current increase was observed in ring oscillators and SRAMs in 28 nm CMOS technology exposed to ultra-high doses. Enhanced Temperature Irradiation (ETI) on isolated devices is used to evaluate the dependence of ELDRS on bias conditions, device size, and threshold voltage. The results obtained show that irradiation at high temperature can represent reasonably well the enhanced degradation induced by low dose rates, providing a viable solution for accelerated radiation tests. The radiation response of MOS transistors in a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high TID was investigated. The investigation revealed that performance is significantly affected by TID, with the radiation response being dominated by the charge trapped in the buried oxide. Despite the techniques used to mitigate TID effects, the 22 nm FDSOI did not prove suitable for application in the inner parts of detectors. However, it could be suitable for applications with lower TID levels.