System design and prototyping of the CMS Level-1 Calorimeter Trigger at the High-Luminosity LHC

The High-Luminosity LHC (HL-LHC) project offers a very ambitious physics program that includes high-precision measurements of the Standard Model (SM) and the searches for new physics beyond the SM (BSM). The efficient data collection and precise events reconstruction in the harsh environment of 200 proton-proton interactions per bunch crossing are vital for achieving the success of the HL-LHC program. To fulfill these requirements, the CMS experiment plans to build and install completely new data acquisition (DAQ) and trigger systems during the so-called CMS Phase-2 upgrade. The Phase-2 CMS Level-1 calorimeter trigger system will handle the enormous detector input data bandwidth of 75 Tbps and is desired to complete the single event processing within 12.5 µs. For this purpose, CMS plans to replace the Phase-1 µTCA-based processor boards and crates with an ATCA form factor. Each ATCA board will host Xilinx UltraScale+ family FPGA that supports over a hundred high-speed optical links at 25 Gbps, capable of meeting the high bandwidth and processing requirements of the HL-LHC. Along with the advancement in hardware, the Level-1 trigger system will employ highly modular, flexible, and adequately sophisticated algorithms currently possible only in offline reconstruction, such as a particle-flow algorithm. The modular and flexible architecture will help to address the HL-LHC physics requirements. In this thesis, we will discuss the system design, prototyping, and algorithms being developed for the Phase-2 Level-1 Calorimeter trigger system.