Development and demonstration of a CMS Phase-2 Level-1 trigger Data Scouting baseline system for HL-LHC

The CMS Phase-2 upgrade for the High-Luminosity LHC introduces the Level-1 Data Scouting (L1DS), a novel data acquisition system that captures and processes Level-1 (L1) trigger information at the full 40 MHz collision rate. The L1DS bypasses the L1 selection to enable searches for signatures previously limited by L1 constraints. This contribution presents the development of a Phase-2 L1DS demonstrator system. A DAQ-800 custom FPGA board performs the L1 data readout and zero-suppression. Pre-processed data is transmitted to a server cluster for event building and online analysis. Validation is done on simulated collisions and running rare Standard Model decay analyses.

The CMS experiment upgrade for the High-Luminosity LHC (HL-LHC), referred to as CMS Phase-2, will significantly extend the capabilities of its Level-1 (L1) trigger system under increased pileup conditions. Advanced algorithms implemented directly in the L1 FPGA processors will select collision events at a 40 MHz bunch crossing rate, with an output rate budget of around 750 kHz and a maximum latency of approximately 11 us. As part of this upgrade, a novel data acquisition system, known as L1 Data Scouting (L1DS), is introduced with the aim to capture and process the L1 reconstructed information at the full collision rate. By leveraging an L1 reconstruction approaching the offline resolution level and bypassing the L1 selection, the L1DS will enhance or enable searches for physics signatures previously constrained by latency and resource limitations.
To validate the proposed L1DS architecture for CMS Phase-2, a demonstrator has been developed and evaluated. The system demonstrates the L1 trigger links readout using a DAQ-800 prototype board, developed in the ATCA form factor for the Phase-2 upgrade of the CMS central DAQ. A DAQ-800 board, equipped with two Xilinx Ultrascale+ VU35P FPGAs and 8 GB of High-Bandwidth Memory (HBM) per FPGA, is designed to accept up to 48×25 Gb/s input optical links and output an average bandwidth of 800 Gb/s after moderate zero-suppression of the input data. The board control and monitoring are managed by an embedded software application running on the DAQ-800 Rear Transition Module (RTM), which features a Trenz System-on-Module and a Zynq Ultrascale+ MPSoC.
The zero-suppressed and concentrated L1 data is buffered in the HBM of the DAQ-800 FPGAs prior to transmission via a firmware implementation of the TCP/IP protocol to a cluster of five commercial servers. A receiver application formats the incoming pre-preprocessed L1 data into event fragments. These fragments are then aggregated by an online processing infrastructure running on the same server cluster and developed within the CMS software framework (CMSSW). During this stage, event building is performed, and multiple analysis algorithms are executed in parallel to identify and select events of interest for further study.
This contribution presents the demonstrator architecture, the FPGA firmware design for the DAQ-800 board and resource utilization, and performance results of the online processing. Extensive validation of the system is carried out by sending simulated HL-LHC collision data, recoderded under the CMS Phase-2 detector and L1 trigger conditions, from a Phase-2 L1 back-end board to the DAQ-800. Physics case studies include searches for rare Standard Model boson decays to mesons, whose selection efficiency at L1 would otherwise be significantly limited by hardware and latency constraints.

This work has been [partially] funded by the Eric & Wendy Schmidt Fund for Strategic Innovation through the CERN Next Generation Triggers project under grant agreement number SIF-2023-004.