A VLSI System-on-Chip for Particle Detectors

In this thesis I present a System-on-Chip (SoC) I designed to oer a self- contained, compact data acquisition platform for micromegas detector mon- itoring. I carried on my work within the RD-51 collab oration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electro de, pro cess the data and p erform monitoring tests. The SoC is built around on a custom 8-bit micropro cessor with internal mem- ory resources and emb eds the p eripherals to b e interfaced with the external ADC. Peripherals implement in hardware threshold checking, p edestal sup- pression, waveform recording and histogram building. The CPU has some attractive features for real-time applications: high working frequency, con- stant instruction execution time, short and xed interrupt latency and a tiny logic fo otprint. The pro cessor makes it p ossible to execute in software additional o-line data pro cessing, such as averaging, FWHM calculation and p eak nding. It includes an 8-bit IO bus for interfacing with exter- nal logic and a UART for RS232 communications. The architecture is fully p ortable to any technology for the implementation of digital circuits (e.g. VLSI CMOS or FPGAs). In fact, I implemented and tested a prototyp e in a Virtex-I I Xilinx FPGA and I completed the layout of a standard-cell CMOS 90nm version of system. The p erformance in terms of clo ck frequency and logic resource o ccupation are discussed in the view of the deployment of the system with the detector and of the development of a multi-channel version of the system