ITk-Pixel FELIX/RD53A Read-out Chain Stress Test Preparations

This master thesis describes the development of an FPGA-based emulator setup for performing system and stress tests of the FELIX-based read-out chain components used in the ATLAS Inner-Tracker (ITk) upgrade. The ITk is part of the ATLAS Phase-II upgrade for operation with the High-Luminosity Large Hadron Collider (HL-LHC). The setup emulates 24 lpGBT data aggregator and 168 RD53A frontend instances on the two Xilinx UltraScale+ KCU116 and VCU128 FPGA development boards, to fully populate the 24 fibre links of the FELIX FLX-712 board. The hit data of the RD53A, as well as the general emulator configuration, is uploaded to the two boards over an ad hoc Ethernet network. A software for controlling the boards over this network and for automated testing using the FELIX software components and the YARR DAQ software has been developed. With the setup, single-frontend and multi-frontend scans were performed. The single-frontend scans showed data losses, especially in FELIX device 1. A multi-frontend scan of up to all RD53A instances could be performed, which however showed the same issues. With the setup, a tool to perform all kinds of data transfer assessment studies for the qualification of the final ITk-Pixel DAQ read-out chain has been obtained.