The FPGA-based first level trigger for the NA62 Experiment at CERN SPS.

The main purpose of the NA62 experiment is to measure the branching ratio of the ultra-rare decay $K^{+} \to \pi^{+} \nu \bar\nu$ with a precision of 10%. The intense flux of particles in a rare-event experiment requires a high-performance trigger and data acquisition system, ensuring a high acceptance for the signal events together with a high rejection of the decays accounting for most of the rate. In this work the trigger processor, called Level-0 Trigger Processor (L0TP), of the first level of the NA62 trigger logic is presented. It has been designed to select candidate events at ∼10 MHz input rate coming from seven different sources of data and to reduce the output trigger rate to 1 MHz. It is the only NA62 trigger level implemented in hardware, by the use of programmable logic (FPGA). Data collected by detectors are sent via Gigabit Ethernet connections to the L0TP board. The logic of firmware compares different event configurations with pre-selected masks, sending the result of the computation to all sub-systems. Performances and limitations of the entire system are reported, including a detailed study of the efficiency of detectors participating to the trigger generation. The development of the L0TP has been performed concurrently with the construction of the experiment, growing in complexity from a preliminary version commissioned during the first pilot run in 2014 to the state of the art system used in the 2016 data taking which is presented in this work.