Design and Evaluation of the IBL BOC for the ATLAS Experiment at CERN

In 2013 during a 20 month long shutdown of the LHC the Pixel Detector of the ATLAS Experiment at CERN will be upgraded by inserting a fourth innermost layer between the beam pipe and the current detector. This so called Insertable B-Layer (IBL) will be constructed with 448 of the new FE-I4 chips to handle the readout of the about 12 million pixels provided by the sensors of this layer. The improved architecture and increased bandwidth of these new readout chips requires new off-detector electronics which were decided to be also backwards compatible to the existing system. Hence the VME card pair establishing the optical interface to front-end and data acquisition (BOC) and managing the data processing and calibration (ROD) have been redesigned for the IBL. In this thesis the redesign of the BOC card is motivated and presented. At first the ATLAS Experiment is described and the need to upgrade the Pixel Detector with a new layer is explained. As the readout chip architecture of the current system has flaws preventing its use for the IBL the new FE-I4 is introduced, and with a look at the current off-detector electronics the need for a redesign of it is justified. Starting with the conceptual planning, the redesign process of the BOC card is presented from hard- and firmware development to testing of the first prototypes. The redesigned BOC is based on modern FPGA technology in conjunction with commercial off-the-shelf optical transceiver modules to provide an integration four times higher than the current system, including the flexibility to adjust to different use cases by simply changing the firmware.